module extender(
        input   [31:0]  i_rm,
        input   [ 1:0]  i_rot,
        input   [ 1:0]  i_op,
        input           i_sign,
        output  [31:0]  o_result
);

reg [31:0] rm_rot;

wire [31:0] extb, exth, extx;

always @* begin
        case (i_rot)
                2'b00: rm_rot =  i_rm                    ;
                2'b01: rm_rot = {i_rm[ 7:0], i_rm[31: 8]};
                2'b10: rm_rot = {i_rm[15:0], i_rm[31:16]};
                2'b11: rm_rot = {i_rm[23:0], i_rm[31:24]};
        endcase
end

assign extb = {{24{i_sign&rm_rot[ 7]}}, rm_rot[ 7: 0]};
assign exth = {{16{i_sign&rm_rot[15]}}, rm_rot[15: 0]};
assign extx = {{ 8{i_sign&rm_rot[23]}}, rm_rot[23:16],
               { 8{i_sign&rm_rot[ 7]}}, rm_rot[ 7: 0]};

assign o_result = i_op[0] ? exth : i_op[1] ? extb : extx ;

endmodule
